Multiple Choice Questions on Architecture & Microprocessor - CodeTextPro

MCQ (Multiple Choice Questions) questions on Architecture & Microprocessor.

(i) Which register can interact with the secondary storage?
(a) MAR
(b) PC
(c) IR
(d) R0

(ii) The decoded instruction is stored in
(a) IR 
(b) PC 
(c) Registers 
(d) MDR

(iii) The fastest data access is provided using

(a) Caches 
(b) DRAM’s 
(c) SRAM’s 
(d) Registers

(iv) ISP stands for
(a) Instruction Set Processor 
(b) Information Standard Processing

(c) Interchange Standard Protocol 
(d) Interrupt Service Procedure

(v) The binary address issued to data or instructions is called as
(a) Physical address 
(b) Location

(c) Relocatable address 
(d) Logical address

(vi) The internal components of the processor are connected by
(a) Processor intra-connectivity circuitry 
(b) Processor bus
(c) Memory bus 
(d) Rambus

(vii) The DMA transfers performed by a control circuit is called
(a) Device interface 
(b) DMA controller
(c) Data controller 
(d) Overlooker

(viii) The number of successful accesses to memory stated as a fraction is called as
(a) Hit rate 
(b) Miss rate
(c) Success rate 
(d) Access rate

(ix) 8085 microprocessor operates at a frequency of
(a) 6 MHz 
(b) 3.2 MHz 
(c) 5 MHz 
(d) 3 MHz

(x) The type of control signal is generated based on
(a) contents of the step counter 
(b) Contents of IR
(c) Contents of condition flags 
(d) All of the above

(xi) READY is used for

(a) Input 
(b) Output 
(c) Both (a) and (b) 
(d) None of these

(xii) Which stack is used in 8085?
(a) FIFO 
(b) LIFO 
(c) FILO 
(d) None of these

(xiii) What is the vector call location of NMI?
(a) 002C H 
(b) 0028 H 
(c) 0010 H 
(d) 0024 H

(xiv) What is a SIM?
(a) Select Interrupt Mask 
(b) Sorting Interrupt Mask
(c) Set Interrupt Mask 
(d) None of these

(xv) RST 7.5 interrupt is
(a) Vectored & Maskable 
(b) Vectored & Non-Maskable
(c) Direct & Maskable 
(d) Direct & Non-Maskable

(xvi) Address line for RST 3 is
(a) 0020H 
(b) 0018H 
(c) 0081H 
(d) None of these

(xvii) If DMA request is sent to the microprocessor with a high signal to the HOLD pin, the microprocessor acknowledges the request
(a) after completing the present cycle 
(b) immediately after receiving the signal
(c) after completing the program 
(d) none of these

(xviii) Which of the following is a user-programmable register?
(a) Memory Address Register 
(b) Accumulator
(c) Program Counter 
(d) All of these

(xix) Select the invalid instruction
(a) MOV M, A 
(b) ADI 67 
(c) LDAX B 
(d) STAX H

(xx) The interrupt line having the highest priority is
(a) RST 7.5 
(b) READY 
(c) TRAP 
(d) INTR

(xxi) The address line required for 16 KB memory chip is
(a) 13 
(b) 14 
(c) 15 
(d) 16

(xxii) A hard disk with 20 surfaces will have _____ heads.
(a) 10 
(b) 5 
(c) 1 
(d) 20

(xxiii) Which among the following is Volatile?

(a) ROM 
(b) EPROM 
(c) DROM 
(d) RAM

(xxiv) Where the result of arithmetic and logical operation are stored?
(a) In Accumulator 
(b) In Cache Memory
(c) In ROM 
(d) In Instruction Registry

(xxv) Which determines the address of I/O interface?
(a) Register select 
(b) Chip select

(c) Both of the above 
(d) None of the above

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