Instruction Cycles | Computer Organization and Architecture

 Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of instructions. These instructions are executed by the processor by going through the each and every instruction.

Instruction Cycle - I:

An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from boot up to when the computer is shut down.

The circuits used in the CPU during the cycle are:

• Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next.

• Memory Address Register (MAR) - holds the address in memory of the next instruction to be executed.

• Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory.

• Instruction register (IR) - a temporary holding ground for the instruction that has just been fetched from memory.

• Control Unit (CU) - decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates activation of those resources.

• Arithmetic logic unit (ALU) - performs mathematical and logical operations.

Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle:

1. Fetch the instruction

The next instruction is fetched from the memory address that is currently stored in the Program Counter (PC), and stored in the Instruction register (IR). At the end of the fetch operation, the PC

points to the next instruction that will be read at the next cycle.

Clock Pulse: T0-T1

2. Decode the instruction

The decoder interprets the instruction. During this cycle the instruction inside the IR (instruction register) gets decoded.

Clock Pulse: T2

3. Read the effective address

In case of a memory instruction (direct or indirect) the execution phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory, and any required data is fetched from main memory to be processed and then placed into data registers (Clock Pulse: T3). If the instruction is direct, nothing is done at this clock pulse. If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse: T3.

Clock Pulse: T3

4. Execute the instruction

The CU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from

registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU.

Clock Pulse: T3-T6 (Up to T6)

The result generated by the operation is stored in the main memory, or sent to an output device. Based on the condition of any feedback from the ALU, Program Counter may be updated to a different address from which the next instruction will be fetched.

The cycle is then repeated.

The Instruction Cycle

Instructions are processed under direction of the control unit in step-by-step manner. Each step is referred to as a phase. There are six fundamental phases of the instruction cycle:

1. fetch instruction (aka pre-fetch)
2. decode instruction
3. evaluate address (address generation)
4. fetch operands (read memory data)
5. execute (ALU access)
6. store result (writeback memory data)

Instruction Cycle - II:

1. Fetch Instruction Phase

• Obtain next instruction from memory.
• Load instruction into instruction register IR.
• MAR is loaded with instruction pointer.
• The instruction is loaded through the MDR.
• Increment processor counter PC, that is, update instruction pointer address while reading instruction from memory.

Memory Circuitry:

Memory Operations:

2. Decode Instruction Phase

• Decoder circuit examines opcode of the instruction.
• Result is selecting unique decoder output line.
• Output line signals a circuit which implements the corresponding operation.

Instruction decoder:

3. Evaluate Operand Address Phase

Compute address of the memory location of the instruction operand.

4. Fetch Operands Phase

• Load MAR with address calculated.
• Read memory into MDR, making data available as input to the processing unit.

5. Execute phase

Microcode for the instruction, selected by the decoder output line, is executed by the ALU.

6. Store Result Phase

• Result is written to the designated destination of the instruction operand.
• Instruction Cycle begins anew.

Steps in a Typical Read Cycle

1. Place the address of the location to be read on the address bus via MAR.

2. Activate the memory read control signal on the control bus.

3. Wait for the memory to retrieve the data from the addressed memory location.

4. Read the data from the data bus into MDR.

5. Drop the memory read control signal to terminate the read cycle.

Steps in a Typical Write Cycle

1. Place the address of the location to be written on the address bus via MAR.

2. Place the data to be written on the data bus via MDR.

3. Activate the memory write control signal on the control bus.

4. Wait for the memory to store the data at the addressed location.

5. Drop the memory write control signal to terminate the write cycle.